1. Field of the Invention
The present invention relates to a phase locked loop oscillating circuit-called hereinafter a PLL circuit.
2. Description of the Prior Art
Usually, a conventional TV receiver uses a PLL circuit as a circuit to generate synchronous pulses with a frequency, which is synchronized, for example, with a horizontal synchronizing signal included in the complex video signal received and which is predetermined upon necessary correction for eventual variation to a certain degree in the frequency of this horizontal synchronizing signal. FIG. 1 shows a block diagram of a typical conventional PLL circuit 1, and the description below will be made by reference to this FIG. 1. This PLL circuit 1 is provided with a phase comparator circuit 2, into which, for example, a horizontal synchronizing signal H separated from the received complex video signal is fed. This phase comparator circuit 2 is equivalent to a three-state buffer 3, which is fed with sychronizing pulses SP1 obtained by dividing, with a divider 9, the synchronizing pulse SP given by a voltage-controlled oscillator (called hereinafter oscillator) 4 included in the PLL circuit 1 and which emits a phase difference signal PD as exhibited on the following truth table.
TABLE 1 ______________________________________ Input Output ______________________________________ H SP PD H High impedance L H H L L L ______________________________________
The phase difference signal PD is fed to a mute adjusting circuit 5, which converts the signal into a phase difference signal PD1, as described later, and feeds it to an active low-pass filter (called hereinafter LPF) 6, where the high frequency components are removed and the filtered voltage DV is fed to the oscillator 4.
The mute adjusting circuit 5 has a resistor R1, a variable resistor VR, and a resistor R2 connected in series, wherein one end of the resistor R1 is grounded while the other end of the resistor R2 is connected with the reference voltage VO (for example 5 V). The LPF 6 includes a resistor R3 in series connection with the mute adjusting circuit 5 and an inverter circuit 7 connected in parallel with a series circuitry of resistor R4 and capacitor C1 and also with a capacitor C2. The inverter circuit 7 is formed as an integrated circuit in which the CMOS (complementary metal oxide semiconductor) technique is incorporated.
The time chart for the fundamental operating condition of the phase comparator circuit 2 is shown in FIGS. 8(1)-8(3) which will also be referred to in description of preferred embodiments. The phase difference signal PD in FIG. 8(3) is obtained by subjecting the level of the synchronizing pulse SP1 while synchronizing signal H in FIG. 8(1) is at Low level, to the level change indicated in Table 1. While the synchronizing signal H is at High level, the three-state buffer 3 shall be in high impedance condition, and the phase difference signal PD is set to the level of the bias voltage VB to be set by the mute adjusting circuit 5.
In case there is no phase difference between the synchronizing pulse SP1 and synchronizing signal H, that is in the condition that the synchronizing pulse SP1 will be switched over from Low to High level at the time t3 as TL/2 has passed from the time t1, where TL represents the Low level period from time t1 to time t2 of the synchronizing signal H as presented in FIG. 8(1), so the phase difference signal PD will be pulses with a duty cycle of 50% as shown in FIG. 2. The center value of the phase difference signal PD has the same level as the bias voltage VB (2.5 V) if the amplitude is selected to VO/2=2.5 V.
At this time, the PLL circuit 1 has the same duty cycle in its range below the bias voltage VB as the one above it, and thus the same frequency range can be used as the correctable range in both cases where the frequency of the synchronizing signal H varies from this condition to the high frequency side and to the low frequency side.
In case the input voltage Vin of the LPF 6 must be varied, the function to adjust the bias voltage VB of the phase difference signal PD1 is accomplished by the mute adjusting circuit 5. That is, the inverter circuit 7, used in the LPF 6, is realized as an integrated circuit according to the CMOS technique as described, and the threshold voltage which serves in determining whether the input voltage is at High or Low level, may vary element by element.
FIG. 3 is a graph exhibiting the input/output voltage relation of an LPF 6 having such an inverter circuit 7 as realized as an integrated circuit due to CMOS technique, wherein the line l1 corresponds to the case with proper threshold voltage while the line l2 corresponds to the case with improperly low threshold voltage, and the line l3 corresponds to the case with improperly high threshold voltage. When an integrated circuit element having such a proper threshold as presented by the line l1 is used as the inverter circuit 7 of the LPF 6, setting the center value of the phase difference signal PD1 to 2.5 V will cause emission of an output Vout=2.0 V in response to Vin=2.5 V in FIG. 3.
In case, by contrast, an integrated circuit element having a characteristic presented by the line l2 is used as the inverter circuit 7, acquisition of the same output voltage Vout=2.0 V involves adjustment for the input voltage Vin=2.0 V by the mute adjusting circuit 5. By this adjustment the phase difference signal PD becomes a signal obtained from the bias voltage VB turned into 2.0 V, shown by the broken line in FIG. 2. Accordingly the area SH of the portion above the new bias voltage VB=2.0 V will become larger than the area SL below the bias voltage VB, and in response thereto the output frequency of the oscillator 4 will vary to cause delay of the synchronizing pulse SP1 in the phase from the synchronizing signal H, as shown by the two-dotted chain line in FIG. 8(2). This gives the phase difference signal PD the same area S1 below the new bias voltage VB=2.0 V as the area SH above it, as indicated in FIG. 4, and the oscillator 4 will now output synchronizing pulses SP which are synchronous with the synchronizing signal H.
In the case that an integrated circuit element having a characteristic presented by the line l3 in FIG. 3 is used as the inverter circuit 7, acquisition of the same output voltage Vout=2.0 V involves adjustment for the input voltage Vin=3.0 V by the mute adjusting circuit 5. By this adjustment the phase difference signal PD becomes a signal obtained from the bias voltage VB turned into 3.0 V, shown by the two-dotted chain line in FIG. 2. Accordingly the area SL of the portion below the new bias voltage VB=3.0 V will become larger than the area SH above the bias voltage VB, and in response thereto the output frequency of the oscillator 4 will vary to cause advance of the synchronizing pulse SP1 in phase from the synchronizing signal H, as shown by the three-dotted chain line in FIG. 8(2). This gives the phase difference signal PD the same area SL below the new bias voltage VB=3.0 V as the area SH above it, as indicated in FIG. 4(2), and the oscillator 4 will now output synchronizing pulses SP which are synchronous with the synchronizing signal H.
The phase difference signal PD with a waveform as indicated in FIG. 4(1) is provided with a deviation that the duty cycles of the portions below and above the bias voltage VB are 60% and 40%, and the phase difference signal PD indicated in FIG. 4(2) is provided with a deviation that the duty cycles of the portions below and above the bias voltage VB are 40% and 60%, respectively, which allows the PLL circuit 1 to be set with different correction ranges for the case in which the synchronizing signal H shifts to a higher frequency side than the synchronizing pulse SP1 and the case of shifting to the lower frequency side. Use of this type of PLL circuit 1 in, for example, a TV receiver does not permit attainment of necessary correction range for varying frequency as specified, to result in generation of such a phenomenon as turbulence in the picture.
In case of further turbulence of the synchronizing signal H causes feeding of noise, pulse PD in FIG. 1 has added noise pulses 8 which are VO=5 or 0 V, as seen in FIG. 5, and the center value of the time average of the noise 8 will be 2.5 V. Use of an integrated circuit element having a proper threshold according to the line l1 in FIG. 3, at this time, for the inverter circuit 7 will give a bias voltage of 2.5 V to be set by the mute adjusting circuit 5, which is in good agreement with the center value of the noise. Use of an inverter circuit 7 having a threshold according to the line l2 in FIG. 3, on the contrary, allows the center value to be set to 2.0 V, as described above, after adjustment by the mute adjusting circuit 5. On the other hand, since the center value of the noise is 2.5 V, the center value as the time average of the whole waveform of phase difference signal PD become 2.25 V which is a median value of the center value of 2.0 V and 2.5 V mentioned above. Wherein in case the eliminated noise 8 causes feeding of the proper synchronizing signal H as shown in FIG. 9 to put the PLL circuit 1 into operation, a problem still remains that the center value will shift immediately from abovementioned 2.25 V to 2.0 V to cause oscillator 4 to output synchronizing pulses SP with different oscillating frequency between the state of noise 8 and the state of proper synchronizing signal.